Roles and Responsibilities

• Develop and maintain verification testbenches for SoC-level simulation and validation
• Create detailed verification plans based on design specifications and architectural documents
• Implement and run directed and constrained-random tests using SystemVerilog and UVM
• Debug RTL and gate-level simulations to identify and resolve design and testbench issues
• Contribute to regression testing, coverage analysis, and sign-off activities
• Work closely with cross-functional teams including design, DFT, and firmware engineers
• Support post-silicon bring-up and validation when required

Requirements

• Strong experience in SystemVerilog and UVM for verification of digital designs
• Deep understanding of SoC architecture, buses (e.g., AXI, AHB), and peripheral IPs
• Experience in writing test cases, assertions, and functional coverage models
• Familiarity with simulators such as VCS, Questa, or Incisive
• Hands-on experience with scripting languages like Python, Perl, or Shell for automation
• Exposure to version control and bug tracking tools
• Ability to analyze and debug waveform dumps and simulation failures