THE ROLE:

The focus of this role in the AECG ASIC organization is to play a key role in driving project success across architecture, design, verification, and physical design. You ll collaborate with cross-functional teams, tackle different problems with diligence for next generation ASICsthat meet Engineering, Business and Customer requirements with best PPA.

THE PERSON:

The ideal candidate will have a strong interest in Architecture, Digital Logic Design and Verification, Design for Test, Synthesis, Static Timing Analysis, Power Verification and optimization, Physical Design aspects like Floorplan, Full chip timing, Place and Route and Utilization experiments. While we do understand that it is very difficult to have knowledge on expected areas, the candidate should have strong foundation in digital design to pick up the necessary concepts and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or any pre-silicon technical issue. You should be able strike a balance between collaborative problem-solving and independent solution development.

KEY RESPONSIBILITIES:

• Study both high-level and micro-architecture specifications to gain an in-depth understanding of new features or changes proposed in new projects.
• Developing micro-architecture specifications and refining execution methodologies for cutting-edge chip designs.
• Work with Architecture/RTL/DFT teams for having optimal design.
• Technical lead on AECG ASIC solutions, tackling problems across domains with focus on driving the best Power, Performance, Area with quality silicon for customers.
• Manage and monitor changes in the given tasks as project matures and be quick to re-align with new or different requirements.
• Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase.
• Work with technology/PD teams to drive signoff margins, reliability related analysis for ASIC use cases.
• Develop technical relationships with broader AMD Design/CAD community and peers.

PREFERRED EXPERIENCE:

• Strong understanding of development of custom ASICs for external customers.
• Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design.
• Strong understanding of SoC Architecture and Digital Design concepts.
• Strong background in STA, Clocks and Power optimization techniques.
• Experience with Verilog or SystemVerilog and UVM
• Knowledge of power management, boot, CPU, AXI Interconnect and I/O peripherals
• Knowledge of PCIE, JESD, CPRI
• Understanding in physical design for PPA optimization.
• Proven track record of delivering SOCs in process technologies 7nm and below.
• Experience in leading a small team of high performing individuals.

EDUCATION & EXPERIENCE:

• Bachelors or Masters degree in in Electrical Engineering or Computer Science. 15+years of experience in ASIC development.