We are seeking a highly experienced DFT (Design for Test) Principal MTS to join our AECG SSD ASIC team in Bangalore. The ideal candidate will have a strong technical background and extensive experience in DFT methodologies, particularly in the context of SoC design and development.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Lead DFT Strategy and Implementation
• Develop and execute comprehensive DFT strategies for SoC projects, ensuring robust testability and manufacturability.
• Develop and Optimize Test Architectures
• Design and implement advanced test architectures, including scan insertion, BIST (Built-In Self-Test), LBIST (Logic Built-In Self-Test), and MBIST (Memory Built-In Self-Test), to enhance test coverage and efficiency.
• Collaborate with Cross-Functional Team
• Work closely with design, verification, and physical design teams to integrate DFT requirements seamlessly into the overall design process.
• Lead Cross-Site Collaboration
• Coordinate with teams across multiple locations to ensure cohesive and unified DFT strategies, promoting effective communication and collaboration.
• Create and Validate Test Patterns
• Generate and validate test patterns for both manufacturing and in-field testing, ensuring high-quality and reliable SoC.
• Analyze and Debug Test Failures
• Investigate and resolve test failures, providing innovative solutions to improve test coverage, yield, and overall product quality.
• Conduct Post-Silicon Debugging
• Perform post-silicon debugging to identify and rectify issues in manufactured silicon, ensuring optimal performance and reliability of SoC.
• Mentor Junior Engineers
• Provide guidance and mentorship to junior engineers, fostering their development in DFT techniques and best practices.
• Stay Updated with Latest Technologies
• Continuously monitor advancements in DFT technologies and methodologies, integrating cutting-edge solutions into the teams workflow.
• Interface with External Vendors
• Collaborate with external vendors and partners to ensure the successful integration of DFT solutions into the manufacturing process.
• Research and Contribute to Patents
• Engage in research activities, publish findings in reputable journals, and contribute to the development of patents in the field of SoC design and DFT methodologies

PREFERRED EXPERIENCE:

• Experience with industry-standard DFT tools and methodologies.
• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
• Understanding various technologies that must work with DFT/DFD technology such as CPU s, memory and I/O controllers, etc
• Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
• Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
• Experience in solving logic design or timing issues with integration, synthesis and PD teams.
• Knowledge of semiconductor manufacturing processes.
• Familiarity with scripting languages such as Python, TCL or Perl.
• Experience with low-power design techniques.
• Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
• Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
• Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

ACADEMIC CREDENTIALS:

• bachelors or masters degree or PhD degree in electrical engineering, Computer Engineering, or a related one.
• 16-20 years of experience in DFT, with a focus on SoC design.
• Proven track record of leading DFT projects from concept to production.
• Deep understanding of DFT techniques such as scan insertion, ATPG, BIST, LBIST, and MBIST.
• Strong problem-solving skills and ability to debug complex test issues.
• Excellent communication and leadership skills.
• Ability to work effectively in a collaborative team environment